Measurement of high frequency signal strength is often required in wireless communication systems. In order to obtain meaningful detection capability for a wide dynamic range in such systems, a linear relationship between output DC voltage/current and input signal power in dBm is desirable. Measurement of output should be insensitive to the input waveform even with a high crest factor, i.e., peak amplitude divided by RMS value.
Optimal operation is dependent upon several factors. Precision measurement of input signal regardless of its waveform over a wide dynamic range of the input signal power is a most important consideration. Fast envelope detection of a modulated input signal is advantageous in obtaining an output that is independent of the input signal waveforms. Linear input impedance vs input power is needed to avoid distortion back to the signal source. As systems often may be subject to considerable temperature variations, stable output should be maintained across the temperature range. Low dc power consumption, of course, is an important objective.
A conventional RMS-to-DC voltage converter is shown in the block diagram of FIG. 1. An a-c signal VIN is applied to X and Y inputs to square cell 20. The square cell output is applied to capacitor 22, which serves to average the voltage applied thereto. Operational amplifier 24 receives the voltage at capacitor 22 and provides the output voltage VOUT. In the absence of a feedback signal to the Z input, the output of the square cell would be a function of the square of the input signal. To obtain an rms value directly corresponding to VIN in such arrangement, output stages would be necessary to perform a square root functionality. As the squared voltages applied to these stages would vary over wide expanded dynamic range of amplitude, the converter would be severely limited to input signals of limited dynamic range. Thus, to expand the dynamic range of the input, the output voltage VOUT is fed back to the Z input of the square cell, which divides the product of the signals applied to the X and Y inputs by the output voltage to perform the square root function prior to averaging. Divided by the average of the output level, the average signal now varies linearly with the rms level of the input, as represented in FIG. 2.
High frequency operation requires the square cell to be biased at reasonable dc quiescent current for all active transistors. The scaling of the biasing current (through Z factor) will significantly degrade the high frequency performance of the square cell (or multiplier XY). However, the magnitude of the dc output signal after the square cell is increased exponentially. For example, an input signal from 10 mV to 1V may be contracted and expanded to 1 mV to 10V at the output of the square cell. In other words, an input signal of 40 dB range is converted to an output signal with 80 dB range. The supply voltage will limit the peak input signal that a square cell can handle due to the headroom of the square cell, as well as subsequent output signal processing. As a result, the converter will have a very limited handling capability for a large input signal. DC offset, caused by device mismatches, will limit the minimum detectable level of the output voltage that can be resolved.
FIG. 3 is a block diagram of a known variation of the converter of FIG. 1 wherein current outputs of balanced square cells 21 and 23 are summed by summing circuit 26. VIN is applied to the input of cell 21. The output of summing circuit 26 is averaged by capacitor 22 and amplified by amplifier 24 to produce the output voltage VOUT, which is applied to the input of cell 23. Summing circuit 26 produces a signal that is the difference between the currents of the square cells.
In summary, the converters of FIGS. 1 and 3 have the following disadvantages. Due to the scaling factor Z applied to the square cell, operation is limited to low frequencies. Due to the closed feedback loop wherein the large Cave of the averaging loop filter sets the loop bandwidth, a slow output response to the input signal change is obtained. Moreover, as the output linearly corresponds to the input, the dynamic range of the converter is limited in comparison with an output that is variable in linear proportion to logarithmic change in RMS voltage of an a-c voltage signal.
Disclosure
The present disclosure overcomes the above-described deficiencies of the prior art. An RMS power to DC converter includes a square cell coupled to an a-c voltage input. A detection circuit is coupled between an output of the square cell and a voltage output node of the converter. The detection circuit includes a plurality of detector cells, each having an output coupled in common with the voltage output node. A plurality of gain cells have outputs that are coupled to inputs of respective ones of the detector cells. The plurality of detector cells may all have substantially the same range of input voltage detection and the gain cells may all have substantially the same gain. The gain cells are coupled in series. At least one of the gain cells is coupled in series between another gain cell and an input of one of the detector cells. The output node of the converter provides a level corresponding to the sum of the outputs of the successive detector stages, the level varying linearly with dB changes in the RMS value of the voltage input.
An attenuation circuit may be coupled between the output of the square cell and a reference potential. An input of a first one of the gain cells is coupled to the output of the square cell. An input of a first one of the detector cells is coupled to an attenuation node of the attenuation circuit. An attenuation stage can thus be cascaded to extend the detection range of the converter for larger input signals. The attenuation circuit may include a plurality of impedances arranged in series, the attenuation node formed as a first attenuation node between a first and second one of the impedances, and a second attenuation node formed between the second one of the impedances and a third one of the impedances. Detector cells are coupled at their inputs to respective attenuation nodes. The first impedance is coupled between the square cell output and the first attenuation node, and may be coupled in parallel with a voltage clamping circuit. A second clamping circuit may be coupled across the second impedance.
In operation, the converter squares the a-c signal to obtain a squared direct current voltage signal. The squared direct current voltage signal is applied to successive stages, each stage amplifying its received signal and detecting the amplified level of the signal within a confined range. The detected levels detected in the successive stages are added to produce an output d-c signal that is variable in linear proportion to logarithmic change in RMS voltage of the input signal. The voltage level of the squared direct current voltage signal can be clamped to a predetermined maximum voltage. To expand the range of detection, the squared direct current voltage signal is attenuated prior to detection in one or more of the stages.
Additional advantages of the disclosed invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated of carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.